1. Field of the Invention
The present invention relates to a burn-in voltage detection circuit for a semiconductor chip, and particularly to an improved burn-in voltage detection circuit for a semiconductor chip capable of detecting a predetermined voltage level related to a burn-in operation using a specific element irrespective of manufacturing variation and advantageously allowing a relationship between a burn-in entry voltage and a burn-in exit voltage to have a predetermined hysteresis characteristic thereby enhancing a normal operation performance thereof and a reliability and stability of a burn-in operation.
2. Description of the Conventional Art
Conventionally, a burn-in operation is performed so as to detect an initial operation defect of a semiconductor chip by applying a predetermined voltage level to a semiconductor chip for a short time and at temperature level higher than that of a normal operation state. An internal voltage generator is in common mounted in a semiconductor chip so as to achieve a lower power consumption and a reliability of the product even in a normal operation, so that the chip can be operable with a predetermined voltage level lower than that of an external voltage applied thereto. The internal voltage generator is directed to maintain a predetermined level of voltage irrespective of a variation of an externally applied voltage in a normal operating state so as to ensure the reliability and operational stability of the chip. Therefore, because a predetermined voltage level higher than that of a normal operation voltage should be applied to all devices in a chip for such a burn-in operation, the internal voltage generator will provide a predetermined voltage level in proportion to a variation of an externally applied voltage when an externally applied voltage exceeds a burn-in entry voltage level. The burn-in voltage detection circuit detects a state where a voltage externally applied to a chip exceeds a predetermined level of a normal operation voltage and reaches to a burn-in entry voltage, and then converts the operation state of the chip into a burn-in operation mode. In addition, in case that an externally applied voltage returns to the normal operation level, the burn-in voltage detection circuit is directed to detect such state and to convert the operational state of the chip into the normal operation mode.
Referring to FIG. 1, a conventional burn-in voltage detection circuit of a semiconductor chip includes a serial array of PMOS transistors 10, in which one side thereof is connected to an externally applied voltage Vdd, an NMOS transistor 11, in which a drain thereof is connected to receive the other side of the PMOS transistor array 10, a source thereof is connected to ground, and a gate thereof receives a reference voltage Vref, a differential amplifier 20 for comparing a voltage outputted from a node N1 connected between the PMOS transistor array 10 and the NMOS transistor 11 with a reference voltage MVA outputted from a reference voltage generating circuit (not shown), a plurality of invertors 30, 40 and 50 in series each inverting an output signal of the differential amplifier 20. Here, a gate of each PMOS transistor of array 10 is connected to its drain.
The differential amplifier 20 includes a pair of PMOS transistors 21 and 22 in which each source thereof is connected to the externally applied voltage Vdd, the gates are connected with each other, and the drains of each is connected to the drain of a corresponding one of a pair of NMOS transistors 23 and 24 described below, an NMOS transistor 23 in which a drain thereof is connected to a drain of the PMOS transistor 21, a source thereof is connected to a drain of an NMOS transistor 25 described below, and a gate thereof receives an output signal of the node N1, an NMOS transistor 24 in which a drain thereof is connected to a drain of the PMOS transistor 22, a source thereof is connected to a drain of the NMOS transistor 25 described below, and a gate thereof receives the reference voltage MVA, and an NMOS transistor 25 in which a drain thereof is commonly connected to each source of the NMOS transistors 23 and 24, a source thereof is connected to ground, and a gate thereof receives a reference voltage BIAS outputted from the reference voltage generating circuit. Here, the gate and drain of the PMOS transistor 21 are connected with each other.
A more detailed operational descriptions of a conventional burn-in voltage detecting circuit is provided below.
When a predetermined voltage Vdd is applied to a semiconductor chip, a voltage MVA which is an internal reference voltage used to drive a memory shell array (not shown), a voltage BIAS which is a predetermined reference voltage for driving an NMOS transistor 25, and a voltage VREF which is a predetermined reference voltage for driving an NMOS transistor 11 are each applied to the burn-in voltage detection circuit. In addition, the reference voltages VREF and BIAS enable the gates of NMOS transistors 11 and 25 to have a predetermined voltage level. At this time, since the NMOS transistor 11 is turned on, the node N1 has a predetermined voltage level Vdd-3.linevert split.Vtp.linevert split. lowered by as much as a threshold voltage Vtp of each of the PMOS transistors of the PMOS transistor array 10.
Therefore, the differential amplifier 20 compares the voltage Vdd-3.linevert split.Vtp.linevert split. of the node N1 applied to the gate of the NMOS transistor 23 with the reference voltage MVA applied to the gate of the NMOS transistor 24 and then outputs a compared result. If the voltage Vdd-3.linevert split.Vpt.linevert split. is smaller than the voltage MVA, the gate-source voltage of the NMOS transistor 23 is smaller than that of the NMOS transistor 24. In this case, the amount of the current flowing toward the transistor 25 through the transistors 22 and 24 is more than that of the current flowing toward the transistor 25 through the transistors 21 and 23. Therefore, the output signal of the differential amplifier 20 is a low level. The output signal of the differential amplifier 20 which is low level is inverted by each of invertors 30 and 40 and outputted as a low level of a signal BINEN signal and outputted as a high level of a signal BINEN through the invertor 50. Thereafter, the semiconductor chip recognizes a current operating state as a normal operation mode and selects an internal voltage using the reference voltage MVA always having a predetermined level of voltage irrespective of a variation of the externally applied voltage and then the internal voltage keeps a predetermined level.
However, if the externally applied voltage Vdd increases and the voltage Vdd-3.linevert split.Vtp.linevert split. becomes higher than the voltage MVA, then contrary to the above, the amount of the current flowing toward the transistor 25 through the transistors 21 and 23 is much more than that of the current flowing toward the transistor 25 through the transistors 22 and 24. Therefore, the output signal of the differential amplifier 20 is a high level. The output signal of the differential amplifier 20 is inverted by each of the invertors 30 and 40 and outputted as a high level of the signal BINEN and outputted as a low level of the signal BINEN through the invertor 50. And then, the semiconductor chip recognizes a current operating state as a burn-in operational mode and then selects a voltage in proportion to a variation of the externally applied voltage Vdd as a reference voltage. As a result, the semiconductor chip is converted into a burn-in operation mode and then the burn-in operation is performed.
However, in the conventional burn-in voltage detection circuit, the burn-in voltage is determined by a threshold voltage of the PMOS transistor array 10. Thereafter, if the threshold voltage Vtp of the PMOS transistor array 10 is varied, then the burn-in voltage is varied therealong. In addition, since the burn-in voltage is adjusted by the threshold voltage Vtp, it is difficult to finely adjust the burn-in voltage.
In addition, when the semiconductor chip is converted into the burn-in operational mode from the normal operational mode, the internal voltage increases much more than in the normal operation and then much more current flows from the externally applied element to the internal element for a short time. Thereafter, the voltage drops due to the resistance components in the semiconductor chip and the voltage applied to the semiconductor chip may be lower than the voltage applied from the externally connected element. In this case, if the lowered external voltage is applied to the burn-in voltage detection circuit, the burn-in voltage detection circuit may mistakenly detect that the external voltage is out of the parameters of the burn-in conditions and then may mistakenly exit from the burn-in operation mode and enter into the normal operation mode. If the operating state of the chip is converted into a normal operating mode, the internal voltage of the semiconductor chip keeps a constant voltage level, so the internal voltage drop is reduced and then it causes the operating state of the chip to be converted once again into the burn-in operation mode, whereby an oscillating state in which the burn-in mode is again converted into the normal operational mode due to the internal voltage level reduction may occur.
In addition, since the NMOS transistors 11 and 25 are always turned on due to the reference voltages VREF and BIAS, the power consumption is increased.